Search - uart VHDL

[Com Port] uart

Description: 采用CPLD实现串口通信（Verilog硬件描述语言）-Realize the use of CPLD serial communication (Verilog Hardware Description Language)
Platform: | Size: 5120 | Author: wuzhidong | Hits:

[VHDL-FPGA-Verilog] UART1

Description: 自己编写的UART模块用VHDL实现，简单实用-I have written UART modules use VHDL realization of simple and practical
Platform: | Size: 3072 | Author: L | Hits:

Description: VHDL语言的UART串行接口芯片程序,包括数据接收器、数据发送器和波特率发生器等。-VHDL language UART serial interface chip procedure, including data receiver, data transmitter and baud rate generator and so on.
Platform: | Size: 3072 | Author: liukun | Hits:

[VHDL-FPGA-Verilog] uart_serial

Description: UART接口的VHDL源代码，成功应用于SOC项目开发中，请勿用于商业用途。-UART interface of the VHDL source code, successfully applied in the development of SOC projects, not for commercial purposes.
Platform: | Size: 12288 | Author: xiaojian | Hits:

[Com Port] uart(Verilog)

Description: RS232的verilog源代码,如果需要的可以-RS232 of Verilog source code, if necessary can be
Platform: | Size: 10240 | Author: 陈强 | Hits:

[VHDL-FPGA-Verilog] uart_exam

Description: VHDL写的串口，很好用，程序非常简单，可以调试用-Written in VHDL serial, very good, and the procedure is very simple, you can debug with
Platform: | Size: 1024 | Author: jimmy | Hits:

[Com Port] uart

Description: 基于MAXII的RS232串口通信程序.还有使用VB编写的上位机串口通信软件。-MAXII based on the RS232 serial communication program. There are prepared to use VB PC serial communication software.
Platform: | Size: 199680 | Author: 张勋 | Hits:

[MPI] uart_dout

Description: 全双工UART口通信程序（Verilog版本）-Full-duplex UART port communication program (Verilog versions)
Platform: | Size: 439296 | Author: 张攀 | Hits:

[VHDL-FPGA-Verilog] uart16550.tar

Description: uart16550 ip core 通用异步收发器vhdl源代码-uart16550 ip core UART VHDL source code
Platform: | Size: 246784 | Author: 姓名 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。-The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.
Platform: | Size: 1106944 | Author: xiao cao | Hits:

[VHDL-FPGA-Verilog] Uart_Send

Description: UART的完整发送程序，包括完整的工程核源代码。-UART to send the complete procedure, including the complete source code of nuclear engineering.
Platform: | Size: 4096 | Author: wanyou2345 | Hits:

[VHDL-FPGA-Verilog] miniUART

Description: 自适应波特率的通用异步串行接口电路（ＵＡＲＴ）的ＶＨＤＬ源码，在ＡＬＴＥＲＡ上运行成功-Adaptive baud rate of the universal asynchronous serial interface circuit (UART) the VHDL source code, to run successfully in ALTERA
Platform: | Size: 9216 | Author: 甘甜 | Hits:

[Crack Hack] micro-UARTsource_V

Description: UART(即Universal Asynchronous Receiver Transmitter 通用异步收发器)是广泛使用的串行数据传输协议。UART允许在串行链路上进行全双工的通信。-UART (ie Universal Asynchronous Receiver Transmitter Universal Asynchronous Receiver Transmitter) is a widely used serial data transfer protocol. UART allows for full-duplex serial link communications.
Platform: | Size: 5120 | Author: 陈 | Hits:

[Com Port] uart

Description: 实现串并口通信,共有发送和接受两个模块。-Strings parallel to achieve communication, send and receive a total of two modules.
Platform: | Size: 1024 | Author: ronin | Hits:

[VHDL-FPGA-Verilog] Intel8251

Description: 用VHDL实现Intel 8251的UART功能-Intel 8251 with VHDL realization of the UART Function
Platform: | Size: 243712 | Author: | Hits:

[Software Engineering] 15Altera_IP

Description: 里面包含15个altera的IP核的源代码,包括I2C，UART，VGA_SYN-Which contains 15 nuclear altera the IP source code, including I2C, UART, VGA_SYN
Platform: | Size: 49152 | Author: hhl | Hits:

[Com Port] pro104_uart

Description: uart的代码，经实际运行可以通信，是xilinx uart 代码的改进，网上的xilinx uart代码有很多bug，用此代码可以改进运行。-UART code, the actual operation can be communication, xilinx uart code are improved, xilinx uart code online has a lot of bug, the code can be improved with this operation.
Platform: | Size: 613376 | Author: max | Hits:

[VHDL-FPGA-Verilog] uart

Description: FPGA的串口模块，实现FPGA与PC机的串口通讯。-FPGA serial modules, FPGA implementation with the PC-Serial communication.
Platform: | Size: 472064 | Author: 王小 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 简单的uart状态机的编写，作为课程设计的资料，适于入门-UART simple state machine to prepare, as a curriculum design information, suitable for entry-
Platform: | Size: 587776 | Author: 李欣 | Hits:

[VHDL-FPGA-Verilog] uart8

Description: 使用Libero提供的异步通信IP核实现UART通信，并附带仿真程序。UART设置为1位开始位，8位数据位，1位停止位，无校验。且UART发送自带2级FIFO缓冲，占用FPGA面积很小。-Libero provided the use of asynchronous communication IP core implementation UART communications, and incidental simulation program. UART is set to 1 to start bit, 8 data bits, 1 stop bit, no parity. UART and send its own two FIFO buffer occupancy is very small FPGA.
Platform: | Size: 876544 | Author: 张键 | Hits:

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[Com Port] uart

[VHDL-FPGA-Verilog] UART1

[VHDL-FPGA-Verilog] VHDL_UART

[VHDL-FPGA-Verilog] uart_serial

[Com Port] uart(Verilog)

[VHDL-FPGA-Verilog] uart_exam

[Com Port] uart

[MPI] uart_dout

[VHDL-FPGA-Verilog] uart16550.tar

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] Uart_Send

[VHDL-FPGA-Verilog] miniUART

[Crack Hack] micro-UARTsource_V

[Com Port] uart

[VHDL-FPGA-Verilog] Intel8251

[Software Engineering] 15Altera_IP

[Com Port] pro104_uart

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] uart8

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